Semiconductor structure having multiple-porous graphene layers and the fabrication method thereof

ABSTRACT

The present invention provides a semiconductor structure having a multiple-porous graphene layer, comprising a semiconductor substrate, a multiple-porous graphene layer, and a gallium nitride layer. And, the present invention provides that the fabrication method for forming the semiconductor structure having a multiple-porous graphene layer, comprises: firstly, growing up the graphene on the copper foil; then, using the acetone and isopropyl alcohol to wash the semiconductor substrate, and then using the nitrogen flow to dry up; transferring the graphene onto the semiconductor substrate, using the Poly(methyl methacrylate)to fix the multiple-porous graphene layer, and using the acetone to wash up; using the photolithography process to etch the whole surface of the multiple-porous graphene layer; and, using the metalorganic chemical vapor deposition to deposit gallium nitride on the multiple-porous graphene layer and the semiconductor substrate.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor structure having a buffer layer, particularly to a semiconductor structure having a multiple-porous graphene buffer layer and the fabrication method thereof.

2. Description of the Prior Art

In the prior art of semiconductor technology field, it is known that during the GaN epilayer growth process, i.e., when the gallium nitride (GaN) is formed on the sapphire semiconductor substrate, there will usually be the disadvantage of lattice mismatch between the formed gallium nitride film and the sapphire semiconductor substrate, and the thermal mismatch of thermal expansion coefficient.

Conventionally, when the gallium nitride epilayer is grown up on the sapphire semiconductor substrate, a buffer layer can be formed under a low temperature condition, before the gallium nitride is formed on the sapphire semiconductor substrate. It is expected that this buffer layer can reduce the big difference of lattice constant and thermal expansion coefficient between semiconductor substrate sapphire and gallium nitride. It can also improve the poor effect caused by the crystallinity, and can further improve the electrical property and optical property of gallium nitride epilayer layer.

However, it is not easy to choose the material as the buffer layer formed on the sapphire semiconductor substrate and there are many various use restrictions, for example, the material shall be able to meet the requirements of lattice constant and thermal expansion coefficient. Thus, in the past studies, it was pointed out that the graphene material seemed to be able to be used as the material of buffer layer formed on the sapphire semiconductor substrate.

After reviewing the past studies, a thicker graphene oxide layer was used to be applied as the intermediate layer. It is applied to the sapphire semiconductor substrate for the growth of gallium nitride epilayer. But, the annealing process is required to reduce the thickness of graphene layer. However, even the annealing process is carried on, the thickness of conventional graphene layer still will be up to 2.2 nm.

In many known materials at present, under room temperature, the graphene has the lowest resistance value, it is also the nano-material with minimum resistivity, and the resistance value of graphene is even lower than copper metal and aluminum metal. The graphene has extremely special properties, such as the thickness of graphene only is a single carbon atom diameter. The graphene also has other special properties, such as high mobility, high current density tolerance, and high thermal conductivity.

In addition, the graphene is undoubtedly a kind of transparent and good elastic conductor, which can receive the favor from the semiconductor industry, it is possible that a large amount of graphene might be applied to the semiconductor field in the future. On the other words, due to the special properties of graphene, it can also cooperate and follow the semiconductor field for the forward development constantly, and create more feasible application examples.

Upon overviewing the current applicable range of graphene, it not only can be applied to the semiconductor field, but also can be applied to the printed circuit boards, transmission wires and cables, mechanical chassis, automobile spare parts, and aviation equipment etc.

Therefore, in the semiconductor process, in order to respond the demand for the development of gallium nitride semiconductor fabrication technology, it is still necessary to develop the relevant gallium nitride semiconductor fabrication technology, to save the fabrication cost, and increase the use efficiency of gallium nitride semiconductor effectively.

SUMMARY OF THE INVENTION

The semiconductor structure having a multiple-porous graphene layer of the present invention comprises a semiconductor substrate, a multiple-porous graphene layer, and a gallium nitride layer.

The semiconductor structure having a multiple-porous graphene layer of the present invention uses three kinds of different structure, the number of graphene layer may be one layer, two layer, and three layers.

The fabrication method for forming the semiconductor structure having a multiple-porous graphene layer of the present invention comprises the following steps: firstly, growing up the graphene on the copper foil by the metalorganic chemical vapor deposition via passing through the methane and hydrogen; then, using the acetone and isopropyl alcohol to wash the semiconductor substrate, and then using the nitrogen flow to dry up; transferring the graphene onto the semiconductor substrate to become the multiple-porous graphene layer by using the ferric chloride as the copper etchant to etch the copper foil, using the Poly(methyl methacrylate) to fix the graphene layer, and using the acetone to wash up; using the photolithography process to etch the whole surface of the multiple-porous graphene layer to form pores; and, using the metalorganic chemical vapor deposition to deposit gallium nitride on the multiple-porous graphene layer and the semiconductor substrate.

As the purpose of using the multiple-porous graphene the present invention, it not only can reduce the problem of lattice mismatch effectively, but also can eliminate the thermal mismatch phenomenon between the gallium nitride and the semiconductor substrate.

The present invention uses the multiple-porous graphene as the buffer layer, which is formed between the gallium nitride and the semiconductor substrate, to increase the quality of gallium nitride epilayer. Due to the high thermal conductivity of graphite itself, it can significantly contribute to the heat dissipation efficiency of the gallium nitride and the semiconductor substrate.

Because the present invention has very high thermal conductivity, the present invention can reduce the defect density caused by the lattice mismatch, and the lattice defect caused by different thermal expansion coefficient, therefore the light emitting efficiency of gallium nitride light emitting diode (LED) can be increased effectively.

The multiple-porous graphene of the present invention has very high thermal conductivity, except there is the advantage of easy heat dissipation, and the graphene can be extensively applied to the fields of LED, solar cell, and high-electron-mobility transistor (HEMT) etc.

And what is worth mentioning, another advantage of the present invention is because the graphene is quite transparent, so when the sandwich structure is made, light still can transport out along the graphene, remain the light emitting effect of LED constantly.

Therefore, the advantage and spirit of the present invention can be understood further by the following detail description of invention and attached FIGS. 1 to 3.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates the cross-sectional diagram for a semiconductor structure having a multiple-porous graphene layer of the present invention;

FIG. 2 illustrates the flow diagram for the fabrication method for forming the semiconductor structure having a multiple-porous graphene layer of an embodiment of the present invention; and

FIG. 3 illustrates the X-ray diffraction result of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The attached figures should be used to describe the implement way of the present invention. In the figures, the same element symbol is used to represent the same element, in order to describe the element more clearly, its size or thickness might be scaled.

Please refer to FIG. 1 that illustrates the cross-sectional diagram for a semiconductor structure 101 having a multiple-porous graphene layer 102 of the present invention. FIG. 1 shows the sapphire semiconductor substrate 101, herein after the silicon semiconductor substrate 101 can also be used. The multiple-porous graphene layer 102 is formed on the silicon semiconductor substrate 101. The gallium nitride layer 103 is formed on the multiple-porous graphene layer 102, wherein the thickness of the multiple-porous graphene layer 102 is 0.345 nm.

FIG. 2 illustrates that the flow diagram for a fabrication method for forming the semiconductor structure 101 having a multiple-porous graphene layer 102 of an embodiment of the present invention. As shown in Step 201 of FIG. 2, firstly, growing up the graphene on the metal foil by the Low Power chemical vapor deposition (LPCVD) at 900° C. to 1100° C., preferably at 1000° C. via passing through the methane (CH₄) and hydrogen (H₂) as the precursor, wherein, the metal foil might be Cu foil or Ni foil.

As shown in Step 202 of FIG. 2, using the acetone and isopropyl alcohol (TPA) to wash the semiconductor substrate 101, and then using the nitrogen flow to dry up.

As shown in. Step 203 of FIG. 2, transferring the abovementioned graphene onto the semiconductor substrate 101 to become the multiple-porous graphene layer 102, using the ferric chloride as the copper etchant to etch the copper foil, using the Poly(methyl methacrylate to fix the multiple-porous graphene layer 102, and using the acetone to wash up.

As shown in Step 204 of FIG. 2, using the photolithography process to etch the whole surface of the multiple-porous graphene layer 102 to form about 50 μm pores for follow-up GaN growth. The thickness of the multiple-porous graphene layer 102 here is about the thickness of one single multiple-porous graphene layer 102, which is about 0.3 nm to 0.4 nm (better thickness is about 0.345 nm). The present invention normally can form one layer, two layers, three layers, and multiple layers of the multiple-porous graphene layer 102 structure. For instance, when the one-layer multiple-porous graphene layer 102 is formed, the thickness is about 0.3 nm to 0.4 nm. When the two-layer multiple-porous graphene layer 102 is formed, the thickness is about 0.6 nm to 0.8 nm. When the three-layer multiple-porous graphene layer 102 is formed, the thickness is about 1 nm to 2 nm. When the multilayer multiple-porous graphene layers 102 are formed, the thickness will be depended on the number of layers.

Finally, as shown in Step 205 of FIG. 2, about 4 μm gallium nitride layer 103 is deposited on the multiple-porous graphene layer 102 and the semiconductor substrate 101 by the MOCVD under at 900° C. to 1100° C., preferably at 1000° C.

As shown in FIG. 3, which illustrates the X-ray diffraction results of the present invention, the present invention is verified that the fabrication method for forming the semiconductor structure 101 having a buffer layer 102 can make the required multiple-porous graphene buffer layer, actually. The multiple-porous graphene buffer layer comprises but not limited to single layer or multiple layers.

The graphene of the present invention has very high thermal conductivity, except there is the advantage of easy heat dissipation, and it can be extensively applied in the fields of LED, solar cell, and high-electron-mobility transistor (HEMT) etc. In addition, what is worth mentioning, another advantage of the present invention is because the multiple-porous graphene is quite transparent, thus, when the sandwich structure is made, light still can transport out along the multiple-porous graphene, remain the light emitting effect of LED constantly.

The present invention uses the multiple-porous graphene as buffer layer, which is formed between the gallium nitride 103 and the semiconductor substrate 101, to increase the quality of gallium nitride epilayer. Due to high thermal conductivity of multiple-porous graphite 102 itself, it can significantly contribute to the heat dissipation efficiency of the gallium nitride 103 and the semiconductor substrate 101. And because the present invention has very high thermal conductivity, it can reduce the defect density caused by lattice mismatch, and the lattice defect caused by different thermal expansion coefficient. Therefore, the light emitting efficiency of gallium nitride light emitting diode (LED) can be increased effectively.

It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains. 

What is claimed:
 1. A semiconductor structure having a multiple-porous graphene layer, comprising: a semiconductor substrate, wherein the semiconductor substrate is selected from the group consisting of a sapphire semiconductor substrate and a silicon semiconductor substrate; a multiple-porous graphene layer is formed on the silicon semiconductor substrate; and a gallium nitride layer is formed on said multiple-porous graphene layer.
 2. The semiconductor structure according to claim 1, wherein a number of multiple-porous graphene layer is selected from the group consisting of one layer, two layers, three layers, and multiple layers.
 3. The semiconductor structure according to claim 2, wherein when one-layer multiple-porous graphene layer is formed, a thickness is between 0.3 nm to 0.4 nm.
 4. The semiconductor structure according to claim 2, wherein when two-layer multiple-porous graphene layer is formed, a thickness is between 0.6 nm to 0.8 nm.
 5. The semiconductor structure according to claim 2, wherein when three-layer multiple-porous graphene layer is formed, a thickness is between 1 nm to 2 nm.
 6. A fabrication method for forming a semiconductor structure having a multiple-porous graphene layer, comprising: growing up a graphene on a metal foil by a low power chemical vapor deposition (LPCVD) via passing through methane (CH₄) and hydrogen (H₂), wherein said metal foil is selected from the group consisting of a Cu foil or Ni foil; using acetone and isopropyl alcohol (IPA) to wash a semiconductor substrate, and using a nitrogen flow to dry up; transferring said graphene onto said semiconductor substrate to become a multiple-porous graphene layer, using a ferric chloride to etch said copper foil, using a Poly(methyl methacrylate to fix said graphene layer, and using acetone to wash up; using a photolithography process to etch a whole surface of said graphene layer to form pores; and using said metalorganic chemical vapor deposition (MOCVD) to deposit gallium nitride on said multiple-porous graphene layer and said semiconductor substrate.
 7. The fabrication method according to claim 6, wherein a number of multiple-porous graphene layer is selected from the group consisting of one layer, two layers, three layers, and multiple layers.
 8. The fabrication method according to claim 7, wherein when one-layer multiple-porous graphene layer is formed, a thickness is between 0.3 nm to 0.4 nm.
 9. The fabrication method according to claim 7, wherein when two-layer multiple-porous graphene layer is formed, a thickness is between 0.6 nm to 0.8 nm.
 10. The fabrication method according to claim 7, wherein when three-layer multiple-porous graphene layer is formed, a thickness is between 1 nm to 2 nm. 